Modern automobiles and other vehicles may include sophisticated on-board computer systems that monitor the status and operation of various components of the vehicle (for example, the vehicle engine, transmission, brakes, suspension, and/or other components of the vehicle). Many of these computer systems may also adjust or control one or more operating parameters of the vehicle in response to operator instructions, road or weather conditions, operating status of the vehicle, and/or other factors.
Various types of microcontroller or microprocessor-based controllers found in many conventional vehicles include supervisory control modules (SCMs), engine control modules (ECMs), controllers for various vehicle components (for example, anti-lock brakes, electronically-controlled transmissions, or other components), among other modules. Such controllers are typically implemented with any one of numerous types of processors that appropriately receive data from one or more sensors or other sources, process the data to create suitable output signals, and provide the output signals to control actuators, dashboard indicators and/or other data responders as appropriate. Such processors may include a main processor for performing these and other functions, and a sub-processor for monitoring the arithmetic logic unit and/or other aspects pertaining to the operation of the main processor.
The processors in a vehicle control system may be periodically or continuously validated for proper operation, often by another processor using a seed and key strategy. While such validation techniques generally perform quite well, in some circumstances the vehicle control system and specified security metrics may not allow for optimal performance of such techniques due, for example, to an increase in validation requirements and/or a decrease in the time and/or memory allotted for doing so. Also, the processors used to validate one another may have different sizes or other features, in which different implementations may be appropriate.
Accordingly, it is desirable to validate the processors more quickly to meet specified security metrics, to reduce memory utilized by such validation techniques, to tailor the validation techniques to the individual processor, and/or to provide improved validation. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.